1. Field of the Invention
The present invention relates to a semiconductor device having a trench isolation structure and a method of manufacturing the same, and particularly to a semiconductor device having a trench isolation structure highly reliable and capable of implementing element isolation of a critical dimension, and a method of manufacturing the same.
2. Description of the Background Art
Recently, with an increasing demand for high integration, a semiconductor device having an element isolation structure of a critical dimension has been required. Conventionally, an LOCOS (Local Oxidation of Silicon) method has been employed as an element isolation method. In isolation by the LOCOS method, however, a bird's beak is formed which makes it difficult to obtain an element isolation of a critical dimension.
Accordingly, a so-called trench isolation technique using a deep narrow trench is focused on as one of element isolation methods capable of implementing element isolation of a critical dimension. One example of the trench isolation technique is disclosed in Japanese Patent Laying-Open No. 60-105247. The trench isolation technique disclosed in Japanese Patent Laying-Open No. 60-105247 will hereinafter be described with reference to FIGS. 50 to 58. FIGS. 50 to 58 are cross sectional views showing an element isolation structure manufactured by the conventional trench isolation technique.
Referring to FIG. 50, a p-type high concentration impurity layer 51 is formed in the main surface of a p-type semiconductor substrate 53, and a p-type low concentration impurity layer 52 is formed on p-type high concentration impurity layer 51. A trench 56 for element isolation is formed in the main surface of p-type semiconductor substrate 53. A polycrystalline silicon layer 60 having p-type impurities introduced is formed in trench 56. An oxide film 58 is formed between polycrystalline silicon layer 60 and the sidewall of trench 56, and a field oxide film 61 is formed at the upper portion of polycrystalline silicon layer 60.
The following effects can be obtained from the above-described structure. Possibility of an inverted layer being provided becomes low, because polycrystalline silicon layer 60 formed in trench 56 has the same potential as p-type semiconductor substrate 53 has, so that the sidewall portion of trench 56 is brought into the state as if a transistor is formed thereon. Specifically, the isolation capability thereof is increased. Additionally, thermal oxidation process is performed for forming field oxide film 61, so that the upper corner portion of polycrystalline silicon layer 60 is simultaneously oxidized, resulting in a rounded shape. Consequently, a substantial distance between the upper corner portion of polycrystalline silicon layer 60 and the sidewall portion of trench 56 becomes longer, whereby formation of an inverted layer due to field concentration at the sidewall portion of trench 56 in the vicinity of the upper corner portion of polycrystalline silicon layer 60 can be effectively prevented. Moreover, polycrystalline silicon layer 60 also has a function to shield an electric field, whereby application of an electric field from an upper wiring to the sidewall of trench 56, and resultant formation of an inverted layer at the sidewall of trench 56 can be effectively prevented.
A method of forming the above-described element isolation structure will now be described with reference to FIGS. 51 to 58. FIGS. 51 to 57 are cross sectional views of the first to seventh steps of the forming process of the above element isolation structure.
Referring to FIG. 51, p-type high concentration impurity layer 51 and p-type low concentration impurity layer 52 are formed, and a silicon oxide film 54 is formed on p-type semiconductor substrate 53 using a thermal oxidation method. p-type impurities are implanted into the main surface of p-type semiconductor substrate 53 through silicon oxide film 54, to form an impurity layer (a channel dope region) 75. A silicon nitride film 55 is formed on silicon oxide film 54.
As shown in FIG. 52, after patterning silicon oxide film 54 and silicon nitride film 55 in a predetermined shape, trench 56 is formed. Through trench 56, boron (B) is diffused in p-type semiconductor substrate 53 to form a p-type high concentration impurity region 57.
As shown in FIG. 53, p-type semiconductor substrate 53 is subjected to thermal oxidation process, so that silicon oxide film 58 is formed on the inner surface of trench 56. As shown in FIG. 54, silicon oxide film 58 is removed only on the bottom surface of trench 56 through etching by an RIE method.
Thereafter, as shown in FIG. 55, a polycrystalline silicon film 59 having boron (B) introduced is formed on the inner surface of trench 56 and silicon nitride film 55. As shown in FIG. 56, polycrystalline silicon layer 60 is etched back so as to be left only in trench 56.
Referring to FIG. 57, field oxide film 61 of a predetermined thickness is formed at the upper portion of polycrystalline silicon layer 60 by thermal oxidation process. At this time, the upper end corner portion of the sidewall of trench 56 is also oxidized. That is, p-type high concentration impurity diffusion layer 57 and impurity layer 75 are oxidized at the upper end corner portion of the sidewall of trench 56. Additionally, in formation of field oxide film 61, p-type impurities are absorbed by field oxide film 61 from p-type high concentration impurity diffusion layer 57 and impurity layer 75 in proximity to field oxide film 61. As a result, the concentration at the upper end corner portion of the sidewall of trench 56 in proximity to field oxide film 61 is reduced.
In order to prevent this, a method can be taken in which impurity layer 75 is formed after forming field oxide film 61. FIG. 58 is cross sectional view showing formation of impurity layer 75 after forming field oxide film 61.
Referring to FIG. 58, even if impurity layer 75 is formed after forming field oxide film 61, p-type impurities for forming impurity layer 75 will not attain a region 81 beneath field oxide film 61, which still results in a low impurity concentration at the upper end corner portion of the sidewall of trench 56 close to field oxide film 61.
Silicon nitride film 55 and silicon oxide film 54 are sequentially removed, whereby the element isolation structure shown in FIG. 50 is formed.
Although the above element isolation structure has a superior isolation capability, there exists the following problem. The problem will be described with reference to FIGS. 59 to 63. FIG. 59 is a perspective view schematically showing an MOS transistor having the conventional element isolation structure described above. FIG. 60 is a cross sectional view taken along the line C--C in FIG. 59. FIG. 61 is an enlarged cross sectional view of the D region in FIG. 60.
Referring to FIG. 59, on a predetermined position of the main surface of a p-type semiconductor substrate 70 is formed an element formation region 72 around which is formed a trench 71 for element isolation. A gate electrode 73 is formed extending on element formation region 72 and trench 71.
The description of a cross sectional structure of the above MOS transistor will be given with reference to FIG. 60. Referring to FIG. 60, p-type semiconductor substrate 70 includes a p-type high concentration impurity layer 70a and a p-type low concentration impurity layer 70b. A trench 71 for element isolation is formed in the main surface of p-type semiconductor substrate 70 so as to attain p-type high concentration impurity layer 70a. Formed in trench 71 is a polycrystalline silicon layer 60 at the upper portion of which a field oxide film 61 is formed. The upper end corner portion of the sidewall of trench 71 is rounded due to formation of field oxide film 61. Gate electrode 73 is formed on trench 71 and element formation region 72, with a gate insulation film 74 interposed therebetween. An n-type impurity region 78 to be a source/drain region is formed on element formation region 72. An MOS transistor 80 is thus structured.
The problem in the MOS transistor having the above-mentioned conventional element isolation structure will now be described with reference to FIG. 61. Referring to FIG. 61, field oxide film 61 is formed by thermal oxidation of the upper portion of polycrystalline silicon layer 60 in the conventional element isolation structure. Therefore, at this time, the upper end corner portion of polycrystalline silicon layer 60 and that of a sidewall 71a of trench 71 are also oxidized, resulting in a rounded shape. Since the upper end corner portion of sidewall 71a of trench 71 is in proximity to field oxide film 61, impurities are absorbed from the upper end corner portion by field oxide film 61 in forming the same. As a result, the p-type impurity concentration of the upper end corner portion of sidewall 71a of trench 71 is reduced.
In the channel region of the MOS transistor of element formation region 72, channel doping is performed for adjusting a threshold voltage of MOS transistor 80 in advance, so that an impurity layer 75 is formed. Impurity layer 75 is formed only in an upper shallow portion of element formation region 72. Therefore, when the upper end corner portion of sidewall 71a of trench 71 has a rounded shape because of thermal oxidation process for forming field oxide film 61 as described above, impurity layer 75 in the vicinity of trench 71 is also oxidized, so that, as shown in FIG. 61, the upper surface of impurity layer 75 is inclined downwardly (in the direction of depth of the trench) in the vicinity of trench 71. Consequently, a region of low impurity concentration where channel doping is not performed exists in a portion opposing gate electrode 73. In the conventional method, therefore, a region 77 having the reduced impurity concentration is formed in the position opposing gate electrode 73 beneath field oxide film 61.
An electric field 76 is applied to reduced impurity concentration region 77 thus formed from gate electrode 73 through field oxide film 61 or gate insulating film 74. At this time, since the upper surface of polycrystalline silicon layer 60 is lower than the main surface of p-type semiconductor substrate 70 as shown in FIG. 61, the electric field 76 from gate electrode 73 can be easily applied to region 77. Such application of the electric field 76 to reduced impurity concentration region 77 from gate electrode 73 results in formation of an inverted layer, i.e. a parasitic transistor.
FIG. 62 is a schematic diagram of an equivalent circuit in the case a parasitic transistor 80a is formed on MOS transistor 80. Referring to FIG. 62, where parasitic transistor 80a is formed because of formation of an inverted layer as described above, a current will flow through parasitic transistor 80a even when no current flows through MOS transistor 80, resulting in a current flow in the circuit including MOS transistor 80. That is, malfunction may be induced. In this case, since parasitic transistor 80a is formed in the region not subjected to channel doping, a parasitic transistor 80a has a low threshold voltage.
FIG. 63 is a graph showing the relation between a voltage (gate voltage Vg) applied to gate electrode 73 of parasitic transistor 80a and MOS transistor 80, and a current (drain current I.sub.D) flowing through the drain region. Referring to FIG. 63, since the threshold voltage of parasitic transistor 80a is low as described above, a current flows through parasitic transistor 80a at a voltage not higher than the threshold voltage (V.sub.th) of MOS transistor 80. The current flow through parasitic transistor 80a thus causes malfunction of MOS transistor 80.
As described above, in the conventional element isolation structure, a parasitic transistor having a low threshold voltage tends to be formed on the upper corner portion of element isolation region 72, whereby such a problem that malfunction of the transistor tends to occur arises. Therefore, an element isolation structure of high reliability cannot be implemented.